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PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
Document Title
512Kx8 Bit High Speed Static RAM(5V Operating). Operated at Extended and Industrial Temperature Ranges.
Revision History
Rev No. Rev. 0.0 Rev. 1.0 History Initial release with Preliminary. 1.1 Removed Low power Version. 1.2 Removed Data Retention Characteristics. 1.3 Changed ISB1 to 20mA 2.1 Relax D.C parameters. Item ICC 12ns 15ns 20ns Previous 170mA 165mA 160mA Current 195mA 190mA 185mA Draft Data Feb. 12. 1999 Mar. 29. 1999 Remark Preliminary Preliminary
Rev. 2.0
Aug. 19. 1999
Preliminary
2.2 Relax Absolute Maximum Rating. Item Voltage on Any Pin Relative to Vss Rev. 3.0 3.1 Delete Preliminary 3.2 Update D.C parameters and 10ns part. ICC 195mA 190mA 185mA Previous Isb 70mA Isb1 20mA ICC 170mA 160mA 150mA 140mA Current Isb 60mA Isb1 10mA Previous -0.5 to 7.0 Current -0.5 to Vcc+0.5 Mar. 27. 2000 Final
10ns 12ns 15ns 20ns
3.3 Added Extended temperature range Rev. 4.0 Delete 20ns speed bin Sep. 24. 2001 Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
512K x 8 Bit High-Speed CMOS Static RAM
FEATURES
* Fast Access Time 10,12,15ns(Max.) * Low Power Dissipation Standby (TTL) : 60mA(Max.) (CMOS) : 10mA(Max.) Operating K6R4008C1C-10 : 170mA(Max.) K6R4008C1C-12 : 160mA(Max.) K6R4008C1C-15 : 150mA(Max.) * Single 5.0V10% Power Supply * TTL Compatible Inputs and Outputs * I/O Compatible with 3.3V Device * Fully Static Operation - No Clock or Refresh required * Three State Outputs * Center Power/Ground Pin Configuration * Standard Pin Configuration K6R4008C1C-J : 36-SOJ-400 K6R4008C1C-T: 44-TSOP2-400BF
GENERAL DESCRIPTION
The K6R4008C1C is a 4,194,304-bit high-speed Static Random Access Memory organized as 524,288 words by 8 bits. The K6R4008C1C uses 8 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNGs advanced CMOS process and designed for highspeed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R4008C1C is packaged in a 400 mil 36-pin plastic SOJ and 44-pin plastic TSOP type II.
FUNCTIONAL BLOCK DIAGRAM
Clk Gen.
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 I/O1~I/O8
ORDERING INFORMATION
K6R4008C1C-C10/C12/C15 Commercial Temp. Extended Temp. Industrial Temp. K6R4008C1C-E10/E12/E15 K6R4008C1C-I10/I12/I15
Pre-Charge Circuit
Row Select
Memory Array 1024 Rows 512 x 8 Columns
Data Cont. CLK Gen.
I/O Circuit Column Select
A10 A11 A12 A13 A14 A15 A16 A17 A18
CS WE OE
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
PIN CONFIGURATION (Top View)
A0 A1 A2 A3 A4 CS I/O1 I/O2 Vcc Vss 1 2 3 4 5 6 7 8 9 10 36 N.C 35 A18 34 A17 33 A16 32 A15 31 OE N.C N.C A0 A1 A2 A3 A4 CS I/O1 1 2 3 4 5 6 7 8 9 44 N.C 43 N.C 42 N.C 41 40 39 38 37 A18 A17 A16 A15 OE
30 I/O8 29 I/O7
36 I/O8 35 I/O7
36-SOJ
I/O2 10 Vcc 11 Vss 12 I/O3 13 I/O4 14 WE A5 A6 A7 A8 A9 15 16 17 18 19 20
28 Vss 27 Vcc 26 I/O6 25 I/O5 24 A14 23 A13 22 A12 21 A11 20 A10 19 N.C
44-TSOP2
34 Vss 33 Vcc 32 I/O6 31 I/O5 30 29 28 27 26 A14 A13 A12 A11 A10
I/O3 11 I/O4 12 WE A5 A6 A7 A8 A9 13 14 15 16 17 18
25 N.C 24 N.C 23 N.C
N.C 21 N.C 22
PIN FUNCTION
Pin Name A0 - A18 WE CS OE I/O1 ~ I/O8 VCC VSS N.C Pin Function Address Inputs Write Enable Chip Select Output Enable Data Inputs/Outputs Power(+5.0V) Ground No Connection
ABSOLUTE MAXIMUM RATINGS*
Parameter Voltage on Any Pin Relative to VSS Voltage on VCC Supply Relative to VSS Power Dissipation Storage Temperature Operating Temperature Commercial Extended Industrial Symbol VIN, VOUT VCC PD TSTG TA TA TA Rating -0.5 to VCC+0.5 -0.5 to 7.0 1.0 -65 to 150 0 to 70 -25 to 85 -40 to 85 Unit V V W C C C C
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70C)
Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Symbol VCC VSS VIH VIL Min 4.5 0 2.2 -0.5** Typ 5.0 0 Max 5.5 0 VCC+0.5*** 0.8 Unit V V V V
* The above parameters are also guaranteed at extended and industrial temperature range. ** VIL(Min) = -2.0V a.c(Pulse Width 8ns) for I 20mA. *** VIH(Max) = VCC + 2.0V a.c (Pulse Width 8ns) for I 20mA.
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70C, Vcc=5.0V10%, unless otherwise specified)
Parameter Input Leakage Current Output Leakage Current Operating Current Symbol ILI ILO ICC VIN=VSS to VCC CS=VIH or OE=VIH or WE=VIL VOUT=VSS to VCC Min. Cycle, 100% Duty CS=VIL, VIN=VIH or VIL, IOUT=0mA Com. 10ns 12ns 15ns Ext. Ind. 10ns 12ns 15ns Standby Current ISB ISB1 Output Low Voltage Level Output High Voltage Level VOL VOH VOH1** Min. Cycle, CS=VIH f=0MHz, CSVCC-0.2V, VINVCC-0.2V or VIN0.2V IOL=8mA IOH=-4mA IOH1=-0.1mA Test Conditions Min -2 -2 2.4 Max 2 2 170 160 150 185 175 165 60 10 0.4 3.95 mA mA V V V Unit A A mA
* The above parameters are also guaranteed at extended and industrial temperature range. ** VCC=5.0V5%, Temp.=25C.
CAPACITANCE*(TA=25C, f=1.0MHz)
Item Input/Output Capacitance Input Capacitance
* Capacitance is sampled and not 100% tested.
Symbol CI/O CIN
Test Conditions VI/O=0V VIN=0V
MIN -
Max 8 7
Unit pF pF
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
AC CHARACTERISTICS(TA=0 to 70C, VCC=5.0V10%, unless otherwise noted.)
TEST CONDITIONS*
Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads
* The above test conditions are also applied at extended and industrial temperature range.
Value 0V to 3V 3ns 1.5V See below
Output Loads(A)
Output Loads(B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ RL = 50 +5.0V
DOUT
VL = 1.5V
ZO = 50 30pF* DOUT 255
480
5pF*
* Capacitive Load consists of all components of the test environment.
* Including Scope and Jig Capacitance
READ CYCLE*
Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Enable to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change Chip Selection to Power Up Time Chip Selection to Power DownTime Symbol tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH tPU tPD K6R4008C1C-10 Min 10 3 0 0 0 3 0 Max 10 10 5 5 5 10 K6R4008C1C-12 Min 12 3 0 0 0 3 0 Max 12 12 6 6 6 12 K6R4008C1C-15 Min 15 3 0 0 0 3 0 Max 15 15 7 7 7 15 Unit ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at extended and industrial temperature range.
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
WRITE CYCLE*
Parameter Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z Symbol tWC tCW tAS tAW tWP tWP1 tWR tWHZ tDW tDH tOW K6R4008C1C-10 Min 10 7 0 7 7 10 0 0 5 0 3 Max 6 K6R4008C1C-12 Min 12 8 0 8 8 12 0 0 6 0 3 Max 6 K6R4008C1C-15 Min 15 10 0 10 10 15 0 0 7 0 3 Max 7 Unit ns ns ns ns ns ns ns ns ns ns ns
* The above parameters are also guaranteed at extended and industrial temperature range.
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC Address tOH Data Out Previous Valid Data
(WE=VIH)
tAA Valid Data
TIMING WAVEFORM OF READ CYCLE(2)
tRC Address tAA tCO tOE OE tOLZ Data out VCC Current ICC ISB
NOTES(WRITE CYCLE) 1. WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device. 5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with CS=VIL. 7. Address valid prior to coincident with CS transition low. 8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
tHZ(3,4,5)
CS
tOHZ
tOH Valid Data
tLZ(4,5) tPU 50% tPD 50%
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE= Clock)
tWC Address tAW OE tCW(3) CS tAS(4) WE tDW Data in High-Z tOHZ(6) Data out High-Z(8) Valid Data tDH tWP(2) tWR(5)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in High-Z tWHZ(6) Data out High-Z(8) Valid Data tOW
(10) (9)
tWR(5)
tWP1(2)
tDH
TIMING WAVEFORM OF WRITE CYCLE(3) (CS = Controlled)
tWC Address tAW tCW(3) CS tAS(4) WE tDW Data in tDH tWP(2) tWR(5)
High-Z
tLZ tWHZ(6)
Valid Data
High-Z
Data out
High-Z
High-Z(8)
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write to the end of write. 3. tCW is measured from the later of CS going low to end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. 6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state. 9. Dout is the read data of the new address. 10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
CS H L L L
* X means Dont Care.
WE X H H L
OE X* H L X
Mode Not Select Output Disable Read Write
I/O Pin High-Z High-Z DOUT DIN
Supply Current ISB, ISB1 ICC ICC ICC
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Rev 4.0 September 2001
PRELIMINARY K6R4008C1C-C, K6R4008C1C-E, K6R4008C1C-I CMOS SRAM
PACKAGE DIMENSIONS
36-SOJ-400
#36 #19
Units:millimeters/Inches
10.16 0.400
11.18 0.12 0.440 0.005
9.40 0.25 0.370 0.010
0.20 #1 #18 0.69 MIN 0.027
+0.10 -0.05
0.008 +0.004 -0.002
23.90 MAX 0.941 23.50 0.12 0.925 0.005 1.19 ) 0.047 1.27 ( ) 0.050 ( 0.43 ( 0.95 ) 0.0375
+0.10 -0.05
3.76 MAX 0.148
0.10 MAX 0.004
0.017 +0.004 -0.002
1.27 0.050
0.71 +0.10 -0.05 0.028 +0.004 -0.002
44-TSOP2-400BF
Units:millimeters/Inches
0~8 0.25 0.010 TYP
#44
#23 0.45 ~0.75 0.018 ~ 0.030
10.16 0.400
11.76 0.20 0.463 0.008
( 0.50 ) 0.020 #1 18.81 MAX 0.741 18.41 0.10 0.725 0.004 1.00 0.10 0.039 0.004 ( 0.805 ) 0.032 0.30 +0.10 -0.05 0.80 0.0315 0.05 0.002MIN 1.20 MAX 0.047 0.10 0.004 MAX #22
0.075 0.125 + 0.035 -
0.005 - 0.001
+ 0.003
0.012 +0.004 -0.002
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Rev 4.0 September 2001

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